1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including a capacitor element, and a method of manufacturing the same.
2. Description of the Related Art
In a semiconductor integrated circuit device, a capacitor element is generally used for decoupling between a power supply and GND, determining a time constant of a circuit, or other such purpose. For example, Japanese Patent Translation Publication No. 2006-503440 discloses an integrated circuit arrangement including a capacitor. The integrated circuit arrangement described in Japanese Patent Translation Publication No. 2006-503440 includes an electrically insulating region and at least one series of regions that form a capacitor, and the capacitor includes an electrode region formed in the vicinity of the insulating region, a dielectric region, and an electrode region formed away from the insulating region in this order. The insulating region is a part of an insulating layer formed in a plane, the capacitor and at least one active element of the rated circuit arrangement are located on the same side with respect to the insulating layer, and the electrode region formed in the vicinity of the insulating region and an active region of the active element are formed in a plane parallel to the plane in which the insulating layer is formed. Here, the active element is preferably a FinFET.
A FinFET is a fin-type field effect transistor, and is a field effect transistor having a three-dimensional structure developed in order to miniaturize a metal oxide semiconductor field effect transistor (MOSFET). A FinFET receives attention as a silicon-on-insulator (SOI) device because of its excellent ability to control channel charge of a gate electrode, and the like.
A FinFET is disclosed in, for example, International Patent WO2006/006424A. The field effect transistor described in International Patent WO2006/006424A includes a semiconductor region which protrudes upward with respect to a plane of a substrate, a cap insulating film provided on an upper surface of the semiconductor region, a gate electrode which extends from above the cap insulating film to a side of the semiconductor region so as to straddle the semiconductor region and the cap insulating film, a gate insulating film interposed between the gate electrode and a side surface of the semiconductor region, and source/drain regions provided in the semiconductor region so as to sandwich a part of the semiconductor region covered by the gate electrode, and a channel region is formed in the side surface of the semiconductor region.
The following analysis is given from the viewpoint of the present invention.
In a case where a capacitor element is provided in a semiconductor integrated circuit device, for example, when a capacitor element is provided in a device including a FinFET, formation of a metal insulator metal (MIM) capacitor element utilizing a metal wiring layer is conceivable. However, in a process of forming the FinFET, usually, a low-permittivity film (low-k film) is introduced as an inter-wiring layer insulating film. Therefore, introduction of a high-permittivity film (high-k film) in order to form a MIM capacitor element increases the process cost.
Therefore, formation of a capacitor element (capacitor) utilizing a FinFET structure is examined. In this case, a gate insulating film of the FinFET is used as a capacitor insulating film of the capacitor element. However, a FinFET is generally a device used with the power supply voltage of 1 V or lower, and an extremely thin gate insulating film (for example, at a thickness of several nanometers) is used. For this reason, in this case, the capacitor insulating film of the capacitor element becomes also extremely thinner. Further, in order to reduce the area, reduction in thickness of the capacitor insulating film is also desired.
When an insulating film is made thinner as in the gate insulating film of a FinFET, because of manufacturing fluctuations, the thickness of the insulating film also fluctuates accordingly. For example, when a fin layer of a FinFET is used as a lower electrode, the thickness of the insulating film is more likely to fluctuate particularly at an end portion (in particular, at an edge portion) of the lower electrode. In addition, the electric field intensity becomes larger at the end portion (in particular, at the edge portion) of the lower electrode. Therefore, when a capacitor element is formed utilizing a FinFET structure, there arises a problem that the time dependent dielectric breakdown (TDDB) life of the insulating film becomes shorter.
In the integrated circuit arrangement described in Japanese Patent Translation Publication No. 2006-503440, the gate insulating film of the active element (transistor) and the insulating film (dielectric film) of the capacitor element (capacitor) are formed in the same process. However, shortening of the TDDB life due to fluctuations in thickness of the insulating film of the capacitor element described above is not at all taken into consideration. Further, in the capacitor element of the integrated circuit arrangement described in Japanese Patent Translation Publication No. 2006-503440, the upper electrode covers the lower electrode and the insulating film. However, shortening of the TDDB life of the insulating film due to electric field concentration at the edge portion of the electrode is not at all taken into consideration.